Physical Design
Physical Design
Synthesis – Logical and physical-aware synthesis
DFT – Advanced scan insertion for robust testability.
Floorplaning – Hierarchical and flat partitioning for efficient chip architecture.
Place & Route – High-performance placement and routing for complex designs.
Clock Tree Synthesis – Balanced, low-skew clock distribution.
Power & EMIR Analysis – Comprehensive power integrity and reliability checks.
Low-Power & LEC – Verification of low-power intent and logical equivalence.
Functional ECOs – Fast and reliable engineering change implementations.
Physical Verification & Signoff – Complete verification for tapeout-ready silicon.
IP Hardening – DDR, MPHY, DPHY, and eMMC PHY integration with proven
reliability.
Full-Chip Delivery – End-to-end physical design for signoff-ready silicon.
Full Chip Physical Design
Top-Level & IO Planning
Bump Planning & Analysis – Optimised bump design for signal and
power integrity.
RDL Routing – Reliable redistribution layer routing from bump to IO
pad (signal/power).
Power Planning – Robust chip-level power distribution strategy.
3rd-Party IP Integration – Seamless integration of external IPs into
top-level design.
IO Pad Placement & Analysis – Signal- and power-aware IO pad
optimization.
IO & Seal Ring Creation – Complete IO ring and seal ring
implementation.
Special Net Routing – Manual routing for sensitive analog and clock
nets.
Core Protection Placement – ESD, TCD, ICOVL, BEOL/FEOL
structures for reliability.
Packaging Collaboration – Close interaction with packaging teams
for end-to-end delivery.
STA
Timing & Signoff Services
SDC Development – Robust constraint creation for accurate
timing analysis.
Top-Level Timing Budgeting – Precise chip-level timing
allocation and management.
SI-Aware Analysis – Noise library–based signal integrity
timing checks.
MMMC Validation – Multi-mode, multi-corner setup and
validation.
Timing Closure – Functional and test-mode closure for
reliable silicon.
Advanced OCV Derates – ΔV and ΔT–based special derate
assessments.
Timing ECOs – Fast implementation for functional, shift,
capture, and BIST modes.